Monolithic and heterogeneous three-dimensional integration of two-dimensional materials with high-density vias | Nature Electronics

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Monolithic three-dimensional (M3D) integration is being increasingly adopted by the semiconductor industry as an alternative to traditional through-silicon via technology as a way to increase the density of stacked, heterogenous electronic components. M3D integration can also provide transistor-level partitioning and material heterogeneity. However, there are few large-area demonstrations of M3D integration using non-silicon materials. Here, we report heterogeneous M3D integration of two-dimensional materials using a dense inter-via structure with an interconnect (I/O) density of 62,500 I/O per mm2. Our M3D stack consists of graphene-based chemisensors in tier 2 and molybdenum disulfide (MoS2) memtransistor-based programmable circuits in tier 1, with more than 500 devices in each tier. Our process allows the physical proximity between sensors and computing elements to be reduced to 50 nm, providing reduced latency in near-sensor computing applications. Our manufacturing process also stays below 200 °C and is thus compatible with back-end-of-line integration.

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Data on samples produced in the 2DCC-MIP facility, including growth recipes and characterization data, are available at https://doi.org/10.26207/f095-ha45. Other data that support the finding of this study are available from the corresponding author on reasonable request.

The codes used for plotting the data are available from the corresponding authors on reasonable request.

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The MOCVD-grown MoS2 monolayer samples were provided by the 2D Crystal Consortium Materials Innovation Platform (2DCC-MIP) facility at the Pennsylvania State University, which is funded by the National Science Foundation (NSF) under cooperative agreement no. DMR-2039351. The authors also acknowledge funding support from the NSF under Award EECS-2042154.

Engineering Science and Mechanics, The Pennsylvania State University, University Park, PA, USA

Subir Ghosh, Yikai Zheng, Zhiyu Zhang, Yongwen Sun, Thomas F. Schranghamer, Najam U Sakib, Aaryan Oberoi, Yang Yang & Saptarshi Das

2D Crystal Consortium Materials Innovation Platform, The Pennsylvania State University, University Park, PA, USA

Chen Chen, Joan M. Redwing & Saptarshi Das

Materials Science and Engineering, The Pennsylvania State University, University Park, PA, USA

Joan M. Redwing

Electrical Engineering, The Pennsylvania State University, University Park, PA, USA

Joan M. Redwing & Saptarshi Das

Materials Research Institute, The Pennsylvania State University, University Park, PA, USA

Joan M. Redwing, Yang Yang & Saptarshi Das

Nuclear Engineering, The Pennsylvania State University, University Park, PA, USA

Yang Yang

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S.D. conceived the idea and designed the experiments. S.G. and Y.Z. fabricated all the 3D chips. S.D., S.G. and Y.Z. performed the experiments, analysed the data, discussed the results and agreed on their implications. C.C. grew the 2D materials under the supervision of J.M.R. Z.Z. and Y.S. performed the focused ion beam and TEM for the 3D chip under the supervision of Y.Y. T.F.S. performed the SEM of the 3D chip. N.U.S. performed the Raman experiment. A.O. performed the AFM measurements. S.G., Y.Z. and S.D. contributed to the preparation of the paper.

Correspondence to Saptarshi Das.

The authors declare no competing interests.

Nature Electronics thanks Sang-Hoon Bae, Xurui Mao and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Schematic showing the M3D stack comprising graphene chemitransistor-based chemisensors in tier 2 connected to MoS2-memtransistor-based comparator in tier 1 for near sensor computing application.

Atomic force microscope (AFM) images and height profiles after (a) fabrication of tier 1 MoS2 devices, (b) post-ILD deposition, and (c) after the via formation and fabrication of tier 2 graphene devices. (d) Surface roughness on top of the ILD over 5 μm × 5 μm area showing a mean roughness of 270 pm.

Output characteristics, that is, source-to-drain current, ${{\rm{I}}}_{{\rm{DS}}}$, versus drain voltage, ${{\rm{V}}}_{{\rm{DS}}}$, at different back-gate voltage, ${{\rm{V}}}_{{\rm{BG}}}$, ranging from 0 to 7 V in steps of 1 V, for a representative MoS2 memtransistor.

(a) Via resistance as a function of via-area. (b) SEM image of the traditional transmission line measurement (TLM) design showing channel lengths of 100 nm, 200 nm, 500 nm, and 1000 nm used to extract the contact resistance. (c) Corresponding transfer characteristics for MoS2 memtransistors obtained from 25 TLM structures. (d) Extracted total resistance (${{\rm{R}}}_{{\rm{T}}}$) as a function of ${{\rm{L}}}_{{\rm{CH}}}$ for an inversion carrier density, ${{\rm{n}}}_{{\rm{s}}}$ = 5 × 1012 cm−2. (e) ${{\rm{R}}}_{{\rm{C}}}$ extracted from the y-intercept of the ${{\rm{R}}}_{{\rm{T}}}$ versus ${{\rm{L}}}_{{\rm{CH}}}$ plots as a function of ${{\rm{n}}}_{{\rm{s}}}$. ${{\rm{R}}}_{{\rm{T}}}$ = ${{\rm{R}}}_{{\rm{CH}}}$ + 2${{\rm{R}}}_{{\rm{C}}}$. ${{\rm{R}}}_{{\rm{CH}}}$ is proportional to ${{\rm{L}}}_{{\rm{CH}}}$ and inversely proportional to the carrier density (${{\rm{n}}}_{{\rm{s}}}$), ${{\rm{R}}}_{{\rm{C}}}$, however, is independent of ${{\rm{L}}}_{{\rm{CH}}}$.

The read current measured at a ${{\rm{V}}}_{{\rm{BG}}}$ of 0 V using a ${{\rm{V}}}_{{\rm{DS}}}$ of 1 V every time after programming a representative MoS2 memtransistor in its high and low conductance states for a total of 1000 cycles. No degradation in the memory ratio (${\rm{MR}}$) highlights the fact that our MoS2 memtransistors offer high endurance.

Transfer characteristics of a representative MoS2-memtransistor-based comparator for different ${{\rm{V}}}_{{\rm{DD}}}$.

Transfer characteristics and extracted distributions for threshold voltage (${{\rm{V}}}_{{\rm{TH}}}$), field-effect mobility (${{\rm{\mu }}}_{{\rm{FE}}}$), and subthreshold swing (${\rm{SS}}$) for 50 MoS2 memtransistors with an ${{\rm{L}}}_{{\rm{CH}}}$ of 500 nm (a) before and (b) after the ILD deposition. We observed a negative 4.5 V shift in the median ${{\rm{V}}}_{{\rm{TH}}}$ value, which can be ascribed to n-type surface charge transfer doping (SCTD) from ALD Al2O3. Additionally, there was an improvement in the median ${{\rm{\mu }}}_{{\rm{FE}}}$ from 3.31 cm2V−1s−1 to 7.27 cm2V−1s−1. However, the median ${\rm{SS}}$ experienced a degradation from 150 mV/dec to 375 mV/dec. Despite these changes, it is important to note that the functionalities of MoS2 memtransistors were not adversely affected. For example, the observed shift in ${{\rm{V}}}_{{\rm{TH}}}$ could be compensated using the programming capability of the FG stack to ensure proper logic levels for the intended applications.

Voltage transfer curves appear complementary when ${\rm{GC}}1$ and ${\rm{GC}}2$ are swapped.

(a) Schematic of a three-stage-inverter-based comparator circuit. Voltage transfer characteristics measured at the output of (b) stage 1, (c) stage 2, and (d) stage 3. Clearly, the gain improves from 172 in stage-1 to 519 in stage-2 to 644 in stage-3. (e) Analogue output voltage (${{\rm{V}}}_{{\rm{Gr}}}$) from graphene chemisensor. Results of digitization at the output of (f) stage 1, (g) stage 2, and (h) stage 3. Clearly, cascading a higher number of inverters to construct the comparator allows better digitization.

Different 2D digital codes generated from the same 4 chemicals (${\rm{C}}1$, ${\rm{C}}2$, ${\rm{C}}3$, and ${\rm{C}}4$) under different ${{\rm{V}}}_{{\rm{LTG}}}$, ranging from 0.2 V to 1.4 V.

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Ghosh, S., Zheng, Y., Zhang, Z. et al. Monolithic and heterogeneous three-dimensional integration of two-dimensional materials with high-density vias. Nat Electron (2024). https://doi.org/10.1038/s41928-024-01251-8

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Received: 29 January 2024

Accepted: 22 August 2024

Published: 09 October 2024

DOI: https://doi.org/10.1038/s41928-024-01251-8

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